David Archer

Principal Scientist, Cryptography & Multiparty Computation

Benjamin Franklin said, “Three can keep a secret, if two of them are dead.” The rising tide of data exfiltration, and the continuing discovery of vulnerabilities in our information security infrastructure, make me deeply interested in how to fill in the missing third leg of information security: keeping information secure while we compute on it, and knowing that the computations we do are exactly the ones we intend. When we compute on data while it remains encrypted (to achieve the former), we need assurance about the latter.

Anton Chekhov said something that rings very true to me: “Knowledge is of no value unless you put it into practice.” So, I’m also very focused on how to bring techniques for achieving these goals into practice for programmers and users that aren’t experts in cryptography.


Dr. Archer has over 30 years of research and development experience in system hardware and software architecture, secure computation, cryptography, and data-intensive systems. Currently, Dr. Archer leads projects in several DARPA programs, including the SafeWare program (cryptographic program obfuscation); the Brandeis program (privacy-preserving computation and databases); and the Transparent Computing program (analysis of computation by its provenance). Dr. Archer also heads research projects for IARPA and the Department of Homeland Security.

At Galois, Dr. Archer leads the company’s research work on secure multi-party computation, applied cryptography, information security, and data provenance. Dr. Archer holds a PhD in Computer Science from Portland State University, and an MS in Electrical Engineering and BS in Computer Engineering from the University of Illinois at Urbana-Champaign.

  • US Patent 9,349,015,“Programmatically Detecting Collusion-Based Security Policy Violations”
  • US Patent 6,148,356,“Scalable Computer System”
  • US Patent 6,021,457,“Method/Apparatus for Minimizing Perturbation While Monitoring Parallel Applications”
  • US Patent 5,634,043,“Microprocessor Point-to-Point Communication”
  • US Patent 5,317,720, “Processor System with Write-back Cache Using Write-back and non Write-back Transactions Stored in Separate Queues”
Recent Conferences and Invited Talks