Current Opening

SoC Physical Design Engineer

Hiring in: Portland, OR, Dayton, OH, and Arlington, VA.

Galois is looking for a passionate and creative individual with a strong technical history and engineering leadership experience to join our expanding SoC Research Team. Our ideal candidate excels at leading SoC Place-and-Route efforts including block implementation, full-chip integration, physical verification, and tapeout. They should also feel comfortable contributing in other areas of SoC development. 

The Work 

As the Senior SoC Physical Design Engineer, you will work on a small talented team of SoC Designers performing research on and implementing novel methodologies and architectures. You will take ownership of the physical design and verification strategy, methodology and execution both at the block level and full-chip. You will have the opportunity to be involved in the full SoC/ASIC design flow – providing input to architecture and front-end design decisions. 

Role/Opportunity Overview  

  • Contribute to a small team of expert SoC designers in all aspects of SoC physical design and verification 
  • Investigate, architect and implement novel back-end SoC methodologies 
  • Provide technical leadership within the team including the training and mentoring of other team members  
  • Opportunity to branch out into adjacent areas such as System Architecture, Front-end Design and Functional Verification.  

Qualifications 

At a minimum, successful candidates have:  

  • Education – Minimum of a Bachelor’s degree in computer science or equivalent. Preference will be given to candidates with an MS or PhD in CS or a related field 
  • 2-5 years SOC Place and Route experience 
  • Experience with Synopsys tools flow including ICC2, ICV 
  • Experience with signoff flows (STA, DRC, LVS) 
  • Solid physical verification debug skills (DRC, LVS, ERC, DFM) 
  • Experience with Synthesis and Static-Timing including constraint development 
  • Ability to create and extend automation flows (RTL to GDSII)  

Preference will be given to candidates with:  

  • 10+ years SOC Place and Route experience 
  • Experience in leadership positions 
  • Experience with RISC-V architecture 
  • Experience in Asynchronous Logic design techniques 
  • Experience in the development of IP for external use 
  • Background in SoC Research  

About Galois 

At Galois we specialize in the research and development of technologies that solve computer science’s most difficult problems. Project teams involve multiple engineers and researchers, likely include team members from academia, industry partners, and government agencies, and range in duration from a few months to several years. Our organizational structure is collaborative, one-level flat, and based on principles of well-defined accountabilities and authorities, transparency, and stewardship. 

We also aspire to provide employees with something that matters to them beyond just a paycheck—whether it be opportunities to learn, career development, a sense of community.

Please click this link to apply.

Position may include access to technology and/or software source code that is subject to U.S. export control requirements under the ITAR or the EAR.